1. Field of the Invention
The present invention relates to a video signal processing circuit and an image pickup apparatus using the circuit. More particularly, the invention relates to a video signal processing circuit and an image pickup apparatus capable of simultaneously changing the number of lines and performing format conversion of video signals by using line memories.
2. Description of Related Art
In an image pickup apparatus such as a digital still camera using a solid image pickup device such as a CCD, an image obtained by the solid image pickup device is displayed on an image display device such as a liquid crystal monitor or a view finder. A user checks an object and a composition by using the displayed image and operates a shutter when a desired image is obtained, thereby capturing the image. In this instance, a digital video signal of the captured still image is written into a recording medium such as a memory card, a magnetic disk, or an optical disk. In such a manner, the image can be acquired without using a film.
By reading the video signal recorded on the recording medium and supplying it to the display device, the obtained still image is displayed on the screen of the display or supplied to a printer or the like wherein the obtained still image is printed. Further, the read video signal is supplied to a computer wherein the obtained still image is processed or the like.
In such a digital still camera, the number of pixels of the solid image pickup device is being increased so as to acquire an image of higher picture quality. In case of using the solid image pickup device having a large number of pixels, when an image for checking the object and the composition (hereinbelow, called a xe2x80x9cpreview imagexe2x80x9d) is displayed on an image display device, it takes time to read a signal since the data amount of the video signals is large. Thereby a motion in the preview image is not smooth. By reading the video signal while thinning out the lines of the solid image pickup device, reduction in the frame rate is prevented.
Since the video signals are read while thinning out the lines, however, a process for changing the image size is performed to display the preview image at a normal aspect ratio.
For example, when images of 30 frames are obtained per second by using a solid image pickup device of 640xc3x97480 pixels, images of 7.5 frames are obtained per second if a solid image pickup device of 1280xc3x97960 pixels is used and the video signal is read at the same speed as that of the solid image pickup device of 640xc3x97480 pixels. Thereby the motion is not smooth. By reading the video signals while thinning out the lines of the solid image pickup device to xc2xc, video signals of an amount corresponding to 30 frames per second can be obtained. Since the video signals of the amount corresponding to 30 frames per second are obtained while thinning out the lines to xc2xc, however, in order to display the preview image at a normal aspect ratio, a process to reduce the image to the half in the horizontal direction and enlarge the image so as to be doubled in the vertical direction is performed.
The process of changing the image size in the vertical direction, that is, the process of changing the number of line is performed by linear interpolation. In the process of changing the number of lines, a process of storing the video signal into a frame memory and changing the number of lines to a desired magnification by using the video signal stored in the frame memory is performed.
By using the frame memory, however, the cost becomes high and it is necessary to assure an area in a substrate to mount the frame memory, so that the miniaturization is hindered. Further, when a frame memory is used for another signal process, the frame memory is shared and it is also used for changing the number of lines, it takes time for the process and the processing speed of the whole system is reduced.
It is an object of the invention to provide a video signal processing circuit capable of easily changing the number of lines with a simple construction at low cost and simultaneously performing a signal format conversion in a real-time manner, and an image pickup apparatus using the circuit.
In carrying out the invention in one preferred mode, I provide a video signal processing circuit comprising first and second line memories for storing an inputted luminance signal, each having a memory capacity larger than a data amount of one line of the luminance signals, and third and fourth line memories for storing an inputted color difference signal, each having a memory capacity larger than a data amount of one line of the color difference signals. Further, the video signal processing circuit comprises first count means for indicating a space line position of each of the luminance signal and the color difference signal to be written in the first to fourth line memories, second count means for indicating a space line position of a luminance signal to be outputted, and third count means for indicating a space line position of a color difference signal to be outputted. The video signal processing circuit also comprises writing and reading means for alternately writing the inputted luminance signal into the first and second line memories every line in a ring method, alternately writing the inputted color difference signal every line into the third and fourth line memories in a ring method, determining a read start position and a read start timing of each of the luminance signals written in the first and second line memories and the color difference signals written in the third and fourth line memories by using integer parts of the first to third count means, and reading the written luminance and color difference signals, and coefficient generating means for generating first to fourth coefficients by using decimal fraction parts of the second and third count means. The video signal processing circuit also comprises a first multiplier for multiplying the luminance signal read from the first line memory by the signal writing and reading means by the first coefficient generated by the coefficient generating means, a second multiplier for multiplying the luminance signal read from the second line memory by the signal writing and reading means by the second coefficient generated by the coefficient generating means, a third multiplier for multiplying the color difference signal read from the third line memory by the signal writing and reading means by the third coefficient generated by the coefficient generating means, a fourth multiplier for multiplying the color difference signal read from the fourth line memory by the signal writing and reading means by the fourth coefficient generated by the coefficient generating means, a first adder for adding outputs of the first and second multipliers to generate a luminance signal whose space line position is shown by the second count means, and outputting the luminance signal, and a second adder for adding outputs of the third and fourth multipliers to generate a color difference signal whose space line position is shown by the third count means, and outputting the color difference signal.
As another preferred mode, I provide an image pickup apparatus comprising image pickup means for obtaining a luminance signal and a color difference signal of an obtained image, first and second line memories for storing the luminance signal obtained by the image pickup means, each having a memory capacity larger than a data amount of one line of the luminance signals, and third and fourth line memories for storing the color difference signal obtained by the image pickup means, each having a memory capacity larger than a data amount of one line of the color difference signals. Further, the image pickup apparatus comprises first count means for indicating a space line position of each of the luminance signal and the color difference signal which are written in the first to fourth line memories, second count means for indicating a space line position of a luminance signal to be outputted, third count means for indicating a space line position of a color difference signal to be outputted. The image pickup apparatus also comprises writing and reading means for alternately writing the inputted luminance signal into the first and second line memories every line in a ring method, alternately writing the inputted color difference signal every line into the third and fourth line memories in a ring method, determining a read start position and a read start timing of each of the luminance signals written in the first and second line memories and the color difference signals written in the third and fourth line memories by using integer parts of the first to third count means, and reading the written luminance and color difference signals, and coefficient generating means for generating first to fourth coefficients by using decimal fraction parts of the second and third count means. The image pickup apparatus comprises a first multiplier for multiplying the luminance signal read from the first line memory by the signal writing and reading means by the first coefficient generated by the coefficient generating means, a second multiplier for multiplying the luminance signal read from the second line memory by the signal writing and reading means by the second coefficient generated by the coefficient generating means, a third multiplier for multiplying the color difference signal read from the third line memory by the signal writing and reading means by the third coefficient generated by the coefficient generating means, a fourth multiplier for multiplying the color difference signal read from the fourth line memory by the signal writing and reading means by the fourth coefficient generated by the coefficient generating means, a first adder for adding outputs of the first and second multipliers to generate a luminance signal whose space line position is shown by the second count means, and outputting the luminance signal, and a second adder for adding outputs of the third and fourth multipliers to generate a color difference signal whose space line position is shown by the third count means, and outputting the color difference signal.
In the invention, the luminance signal is written alternately to the first and second line memories and the color difference signal is written alternately to the third and fourth line memories. During a period of writing the luminance signal of one line or the color difference signal of one line, for example, the luminance signals of one line written in the first and second line memories are read a plurality of times and the color difference signals of one line written in the third and fourth line memories are read only by the number of times which is the half of the number of times of reading the luminance signal. The reading start position and reading start timing of each of the luminance signals written in the first and second line memories and the color difference signals written in the third and fourth line memories are determined by using the integer parts of the first to third count means.
First to fourth coefficients are generated by the coefficient generating means by using decimal fraction parts of the second count means for showing the space line position of a luminance signal to be outputted and the decimal fraction parts of the third count means for showing the space line position of a color difference signal to be outputted. The luminance signal read from the first line memory is multiplied by the first coefficient, the luminance signal read from the second line memory is multiplied by the second coefficient. The two luminance signals multiplied by the coefficients are added, thereby generating a new luminance signal by linear interpolation. The count step amount of each of the second and third count means is varied and the number of lines of luminance signals to be generated is varied according to the count step amount.
Further, during a period in which luminance signals of one line are read twice from the first and second line memories, the color difference signals of one line are read once from the third and fourth line memories. The color difference signal read from the third line memory is multiplied by the third coefficient and the color difference signal read from the fourth line memory is multiplied by the fourth coefficient. The two color difference signals multiplied by the coefficients are added, thereby simultaneously generating new color difference signals of one line per new luminance signals of two lines.
A further understanding of the nature and advantages of the invention may be realized by reference to the following portions of the specification and drawings.